Maximizing memory data reuse for lower power motion estimation
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Methodical Low-Power ASIP Design Space Exploration
Journal of VLSI Signal Processing Systems
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse
Journal of VLSI Signal Processing Systems
Parallel motion estimation on the MDSP multiprocessor
Neural, Parallel & Scientific Computations
Unified convolutional/turbo decoder design using tile-based timing analysis of VA/MAP kernel
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DCT-domain coder for digital video applications
Journal of Real-Time Image Processing
The general matrix multiply-add operation on 2D torus
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Software defined radio – a high performance embedded challenge
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
VLSI implementation of a configurable IP Core for quantized discrete cosine and integer transforms
International Journal of Circuit Theory and Applications
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