Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
Low-Power Implementation of Discrete Cosine Transform
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
Analysis and design of low power digital multipliers
Analysis and design of low power digital multipliers
Image quality assessment: from error visibility to structural similarity
IEEE Transactions on Image Processing
A simple processor core design for DCT/IDCT
IEEE Transactions on Circuits and Systems for Video Technology
Dynamic range analysis for the implementation of fast transform
IEEE Transactions on Circuits and Systems for Video Technology
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Low power consumption in computing systems is a key requirement for devices such as cell phones and cameras. In this paper we present a low power DCT implementation using a highly scalable multiplier. This paper focuses on IDCT with playback applications such as digital photo displays. The proposed solution exploits the fact that the size of the multiplications varies per stage in a multistage IDCT implementation and configuring multipliers to match the needs of each stage saves power. Results are compared with Wallace and Array multipliers. We show that using a scalable multiplier and dynamically reconfiguring the width of the multiplier leads to significant power savings (over 72%) with negligible degradation in decoded image quality.