Computer Vision, Graphics, and Image Processing
Computer arithmetic algorithms
Computer arithmetic algorithms
The image processing handbook
Parameterized convolution filtering in an FPGA
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Digital image processing
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Improving embedded system design by means of HW-SW compilation on reconfigurable coprocessors
Proceedings of the 15th international symposium on System Synthesis
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Image Processing Algorithms on Reconfigurable Architecture using HandelC
DSD '04 Proceedings of the Digital System Design, EUROMICRO Systems
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
OveRSoC: a framework for the exploration of RTOS for RSoC platforms
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
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This paper presents a multi-language framework to FPGA hardware development which aims to satisfy the dual requirement of high-level hardware design and efficient hardware implementation. The central idea of this framework is the integration of different hardware languages in a way that harnesses the best features of each language. This is illustrated in this paper by the integration of two hardware languages in the form of HIDE: a structured hardware language which provides more abstract and elegant hardware descriptions and compositions than are possible in traditional hardware description languages such as VHDL or Verilog, and Handel-C: an ANSI C-like hardware language which allows software and hardware engineers alike to target FPGAs from high-level algorithmic descriptions. On the one hand, HIDE has proven to be very successful in the description and generation of highly optimised parameterisable FPGA circuits from geometric descriptions. On the other hand, Handel-C has also proven to be very successful in the rapid design and prototyping of FPGA circuits from algorithmic application descriptions. The proposed integrated framework hence harnesses HIDE for the generation of highly optimised circuits for regular parts of algorithms, while Handel-C is used as a top-level design language from which HIDE functionality is dynamically invoked. The overall message of this paper posits that there need not be an exclusive choice between different hardware design flows. Rather, an integrated framework where different design flows can seamlessly interoperate should be adopted. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware languages.