Computer arithmetic algorithms
Computer arithmetic algorithms
A Family of Variable-Precision Interval Arithmetic Processors
IEEE Transactions on Computers
A Library of Parameterized Floating-Point Modules and Their Use
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
MIMO Wireless Communications
MPFR: A multiple-precision binary floating-point library with correct rounding
ACM Transactions on Mathematical Software (TOMS)
When FPGAs are better at floating-point than microprocessors
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Introduction to Interval Analysis
Introduction to Interval Analysis
A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Optimising memory bandwidth use for matrix-vector multiplication in iterative methods
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
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In the majority of scientific computing applications, values are represented using a floating point number system. However, this number system only considers an approximate value without any indication of the approximation's accuracy. Interval arithmetic provides a means to ensure that the solution is bounded with absolute certainty. However, whilst interval arithmetic can be applied to any algorithm to ensure bounds on a solution, the limitations of interval arithmetic can lead to bounds that are not always tight and hence not particularly useful. As a result, some algorithms are specifically designed with interval arithmetic in mind to find high quality bounds on a solution; the Krawczyk algorithm is one such algorithm. The Krawczyk algorithm is targeted towards solving systems of linear equations, which is a common problem in scientific computing and has drawn a wide interest in the FPGA community. We show that by accelerating this algorithm in hardware, developing specialised arithmetic units, it is possible to gain orders of magnitude improvement in execution time over a C implementation.