Computer Vision, Graphics, and Image Processing
Computer arithmetic algorithms
Computer arithmetic algorithms
Algorithmic skeletons: structured management of parallel computation
Algorithmic skeletons: structured management of parallel computation
Signed digit arithmetic on FPGAs
Selected papers from the Oxford 1993 international workshop on field programmable logic and applications on More FPGAs
Digital image processing
Prototyping parallel algorithms using standard ML
BMVC '95 Proceedings of the 6th British conference on Machine vision (Vol. 2)
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
A 800 Mpixel/sec reconfigurable image correlator on XC6216
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A CAD Suite for High-Performance FPGA Design
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
From application descriptions to hardware in seconds: a logic-based approach to bridging the gap
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A General-Purpose FPGA-Based Reconfigurable Platform for Video and Image Processing
ISNN 2009 Proceedings of the 6th International Symposium on Neural Networks: Advances in Neural Networks - Part III
Experiencing a problem-based learning approach for teaching reconfigurable architecture design
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
A Comparison Study for a Neural Network Based Embedded Appliance
Proceedings of the 2011 conference on Neural Nets WIRN10: Proceedings of the 20th Italian Workshop on Neural Nets
ARM based microcontroller for image capturing in FPGA design
ISVC'05 Proceedings of the First international conference on Advances in Visual Computing
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In this paper, we present our approach to developing a general framework for FPGA based Image Processing. This framework is based on a library of hardware skeletons. A hardware skeleton is a parameterised description of a task-specific architecture. A skeleton's implementation will apply optimisations specific to the target hardware. The library normally contains a range of alternative skeletons for the same task, perhaps tailored for different data representations. The library also contains high level skeletons for compound operations, whose implementation can apply appropriate optimisations. Given a complete algorithm description in terms of skeletons, an efficient hardware configuration is generated automatically. We have developed a library of hardware skeletons for common image processing tasks, with optimised implementations specifically for Xilinx XC4000 FPGAs. This paper presents and illustrates our hardware skeleton approach in the context of some common image processing tasks. It demonstrates our approach to the broader problem of achieving optimised hardware configurations while retaining the convenience and rapid development cycle of an application-oriented, high level programming model.