Computer arithmetic algorithms
Computer arithmetic algorithms
A robust multiplexer-based FPGA inspired by biological systems
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: dependable parallel computer systems
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Embryonics: The Birth of Synthetic Life
Papers from an international workshop on Towards Evolvable Hardware, The Evolutionary Engineering Approach
Functional Organisms Growing on Silicon
ICES '96 Proceedings of the First International Conference on Evolvable Systems: From Biology to Hardware
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Field-programmable gate arrays
Communications of the ACM
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The crossbreeding between advanced microprocessor design and Field Programmable Gate Arrays (FPGAs) has produced the Field Programmable Processor Array, code named FPPA. The first integrated version has been targeted for low power consumption parallel processing. The FPPA is composed of a 10 麓10 array of RISC microcontrollers offering up to 500 MIPS at 5 MHz for processors (20 MHz for communications). The very low power feature of the core processor results in a 1 Watt power consumption for the whole array at 5 MHz and makes it particularly interesting for portable devices that require quite complex algorithms. In addition, FPPA principle, i.e., fault-tolerant large array of cells interconnected with an asynchronous communication scheme, is applicable on alternative structures for the cell architecture.