Area-time optimal VLSI integer multiplier with minimum computation time
Information and Control
Parallel computations on meshes with static and reconfiguarble buses
Parallel computations on meshes with static and reconfiguarble buses
IEEE Transactions on Computers
Constant time sorting on a processor array with a reconfigurable bus system
Information Processing Letters
Meshes with reconfigurable buses
Proceedings of the fifth MIT conference on Advanced research in VLSI
Proceedings of the conference on CONPAR 88
Journal of Parallel and Distributed Computing
Parallel Computations on Reconfigurable Meshes
IEEE Transactions on Computers
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
IEEE Transactions on Parallel and Distributed Systems
An Optimal Sorting Algorithm on Reconfigurable Mesh
IPPS '92 Proceedings of the 6th International Parallel Processing Symposium
An Efficient Convex Hull Computation on the Reconfigurable Mesh
IPPS '92 Proceedings of the 6th International Parallel Processing Symposium
Area-Time Optimal VLSI Networks for Computing Integer Multiplications and Discrete Fourier Transform
Proceedings of the 8th Colloquium on Automata, Languages and Programming
The Image Understanding Architecture
The Image Understanding Architecture
Constant Time Dynamic Programming on Directed Reconfigurable Networks
IEEE Transactions on Parallel and Distributed Systems
IEEE Transactions on Parallel and Distributed Systems
The implementation of 2D FFT using multiple topology on 4 × 4 torus
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
An algorithm for parallel calculation of trigonometric functions
Proceedings of the ACM International Conference on Computing Frontiers
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An O(1) time algorithm to multiply two N-bit binary numbers using an N脳N bit-model of reconfigurable mesh is shown. It uses optimal mesh size and it improves previously known results for multiplication on the reconfigurable mesh. The result is obtained by using novel techniques for data representation and data movement and using multidimensional Rader Transform. The algorithm is extended to result in AT2 optimality over $1\le T\le \sqrt N$ in a variant of the bit-model of VLSI.