An Optimal Multiplication Algorithm on Reconfigurable Mesh
IEEE Transactions on Parallel and Distributed Systems
A Simple Voronoi Diagram Algorithm for a Reconfigurable Mesh
IEEE Transactions on Parallel and Distributed Systems
Low Power Digital CMOS Design
Digital Signal Processing: A Practical Approach
Digital Signal Processing: A Practical Approach
Implementation of a 2-D Fast Fourier Transform on an FPGA-Based Custom Computing Machine
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Parallel FFT Algorithms on Network-on-Chips
ITNG '08 Proceedings of the Fifth International Conference on Information Technology: New Generations
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In this paper, we proposed 2D FFT for 8 × 8 matrix without transpose of data by using multiple topology on 4 × 4 Torus. The proposed 2D FFT used parallel operation on 1D FFT and applied an effective calculation by executing a pipeline operation. We implement the proposed architecture on Xilinx Virtex-IV device and a detailed evaluation has been reported based on maximum system frequency, chip area and image size. The implementation results show that the core speed of the proposed FFT architecture is around 157.3MHz and it occupies 11733 slices. The average SQNR for various images is 61.9dB. To compare the proposed 2D FFT with other methods, we can see that frame per second is improved 8 times.