A VLSI layout for a pipelined Dadda multiplier

  • Authors:
  • Peter R. Cappello;Kenneth Steiglitz

  • Affiliations:
  • Dept. of Computer Science, University of California, Santa Barbara, CA;Dept. of Electrical Engineering and Computer Science, Princeton University, Princeton, NJ

  • Venue:
  • ACM Transactions on Computer Systems (TOCS)
  • Year:
  • 1983

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Abstract