Area-time optimal VLSI integer multiplier with minimum computation time
Information and Control
VLSI Architectures for Computing Multiplications and Inverses in GF(2m)
IEEE Transactions on Computers
Log depth circuits for division and related problems
SIAM Journal on Computing
Sublinear parallel algorithm for computing the greatest common divisor of two integers
SIAM Journal on Computing
Area-time optimal division for T =Ω((log n)1+ε)*
Information and Computation
The Area-Time Complexity of Binary Multiplication
Journal of the ACM (JACM)
Information transfer and area-time tradeoffs for VLSI multiplication
Communications of the ACM
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Area-Time Optimal VLSI Networks for Computing Integer Multiplications and Discrete Fourier Transform
Proceedings of the 8th Colloquium on Automata, Languages and Programming
The entropic limitations on VLSI computations(Extended Abstract)
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
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VLSI designs for Galois field multipliers, which are central in many encoding and decoding procedures for error-detecting and error-correcting codes, are presented. An AT/sup 2/-optimal Galois-field multiplier based on AT/sup 2/-optimal integer multipliers for a synchronous VLSI model is exhibited. Galois field multiplication is done in two steps. First two polynomials (of degree n-1) over Z/sub p/ are multiplied, and then the resulting polynomial is reduced modulo a fixed irreducible polynomial (of degree n). Multiplication of polynomials is done by discrete Fourier transform (DFT). For p=2, the procedure is more involved for Z/sub p/(x) than for Z(x). An extension to the case of variable p is included and some open problems are stated.