Optimal VLSI architectures for multidimensional DFT (preliminary version)

Authors:
Ginfranco Bilardi;Scot W. Hornick;Majid Sarrafzadeh
Affiliations:
Department of Computer Science, Upson Hall, Cornell University, Ithaca, NY;Andersen Consulting, Center for Strategic Tech. Res., 100 S. Wacker, Chicago, IL;Dept. of Elec. Eng. and Comp. Sci., The Technological Institute, Northwestern University, Evanston, IL
Venue:
ACM SIGARCH Computer Architecture News - Symposium on parallel algorithms and architectures
Year:
1991

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Abstract

A family of VLSI architectures for computing an (n1 × n2 × … × nd)-point multidimensional DFT (MDDFT) over ℤM, the ring of integers modulo M, is presented. These architectures achieve VLSI area A = O ((N2log2M)/T2 for any computation time T ∊ [Ω(logN), O (√NlogM)] where N = ∏dk=1nk and it is assumed that logM = O (logN). A lower bound argument is developed to show that the proposed architectures are area-time optimal. The applicability of these architectures to computation of the MDDFT over the complex field is also discussed. Using fixed-point arithmetic with b bits of precision, their area-time performance is AT2 = O (N2b2) for any computation time T ∊ [Ω(logN), O(√Nb)].