Depth-size trade-offs for parallel prefix computation
Journal of Algorithms
Proc. of the Aegean workshop on computing on VLSI algorithms and architectures
Journal of the ACM (JACM)
Structure of Computers and Computations
Structure of Computers and Computations
The Influence of Key Length on the Area-Time Complexity of Sorting
Proceedings of the 12th Colloquium on Automata, Languages and Programming
Unbounded fan-in circuits and associative functions
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
New bounds for parallel prefix circuits
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
A complexity theory for VLSI
Energy consumption in VLSI circuits
STOC '88 Proceedings of the twentieth annual ACM symposium on Theory of computing
Hi-index | 0.00 |
The prefix problem consists of computing all the products x0x1…xj (j=0, …, N - 1), given a sequence x = (x0, x1, …, xN - 1) of elements in a semigroup. In this paper we completely characterize the size-time complexity of computing prefixes with boolean networks, which are synchronized interconnections of Boolean gates and one-bit storage devices. This complexity crucially depends upon a property of the underlying semigroup, which we call cycle-freedom (no cycle of length greater than one in the Cayley graph of the semigroup). Denoting by S and T size and computation time, respectively, we have S = &THgr;((N/T) log(N/T)), for non-cycle-free semigroups, and S = &THgr;(N/T), for cycle-free semigroups. In both cases, T ∈ [&OHgr;(logN), O(N)].