Computer organization and design (2nd ed.): the hardware/software interface
Computer organization and design (2nd ed.): the hardware/software interface
The MPEG-4 Multimedia Coding Standard: Algorithms, Architectures and Applications
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Instruction Set Extensions for MPEG-4 Video
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
MPEG-4 Video and Image Coding on Digital Signal Processors
Journal of VLSI Signal Processing Systems - Special issue on implementation of MPEG-4 multimedia codecs
Imagine: Media Processing with Streams
IEEE Micro
Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A video display processing platform for future TV concepts
IEEE Transactions on Consumer Electronics
Bandwidth reduction for video processing in consumer systems
IEEE Transactions on Consumer Electronics
Cheops: a reconfigurable data-flow system for video processing
IEEE Transactions on Circuits and Systems for Video Technology
FPGA-oriented HW/SW implementation of the MPEG-4 video decoder
Microprocessors & Microsystems
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The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging from stream-oriented processing to highly data-dependent irregular processing with complex control. This paper presents the mapping of a Main-Visual profile MPEG-4 decoder for High-Definition (HD) video onto a flexible architecture platform. The hardware-software (HWSW) design is derived by analyzing a partitioning of distinct tasks within the application. The proposed implementation contains a hierarchy of processors, which are matched to the characteristics of the processing tasks. Additionally, we introduce a hierarchy in communication and memory for memory-bandwidth efficiency and flexibility for HW reuse. The architecture provides various trade-off possibilities (flexibility, extensibility, HW-SW) while achieving the high performance density (i.e. the performance per unit area per unit power) that is required for consumer systems.