VLSI array processors
A Single-Chip Multiprocessor for Multimedia: the MVP
IEEE Computer Graphics and Applications
Digital Video: An introduction to MPEG-2
Digital Video: An introduction to MPEG-2
Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations
IEEE Transactions on Computers
IEEE Transactions on Computers
A novel four-step search algorithm for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
A cost-effective architecture for 8×8 two-dimensional DCT/IDCT using direct method
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
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This paper presents a parallel architecture that can simultaneously perform block-matching motion estimation (ME) and discrete cosine transform (DCT). Because DCT and ME are both processed block by block, it is preferable to put them in one module for resource sharing. Simulation results performed using Simulink demonstrate that the parallel fashioned architecture improves the performance in terms of running time by 18.6% compared to the conventional sequential fashioned architecture.