Discrete cosine transform: algorithms, advantages, applications
Discrete cosine transform: algorithms, advantages, applications
A high-performance architecture with a macroblock-level-pipeline for MPEG-2 coding
Real-Time Imaging - Special issue on special purpose architectures for real-time imaging
An FPGA-based video compressor for H.263 compatible bit streams
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
FPGA Implementation of the Block-Matching Algorithm for Motion Estimation in Image Coding
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm
EDTC '96 Proceedings of the 1996 European conference on Design and Test
A Flexible H.263 Video Coder Prototype Based on FPGA
RSP '02 Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP'02)
Hardware-software co-implementation of a H.263 video codec
IEEE Transactions on Consumer Electronics
IEEE Transactions on Circuits and Systems for Video Technology
Customizing multiprocessor implementation of an automated video surveillance system
EURASIP Journal on Embedded Systems
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In this paper a flexible and efficient architecture that implements the core of a video coder according to Rec. H.263 is presented. It consists of a RISC processor that controls the scheduling of a set of specialized processors that perform the discrete cosine transform (DCT), the inverse discrete cosine transform (IDCT), the direct and inverse quantization (DQ and IQ), the motion estimation (ME) and the motion compensation (MC). The architecture also includes pre-processing modules for the input video signal from the camera and interfaces for the external video memory and the H.263 stream generation.The processors have been written in synthesizeable Verilog and the firmware for the RISC (a commercial processor) has been developed in C language.The design has been tested with hardware-software co-simulations in a Verilog testbench using standard video sequences and has also been prototyped onto a development system based on an FPGA and a RISC. It performs 30 QCIF frames/s with a system clock of 12 MHz or 30 CIF frames/s with a system clock of 48 MHz, which is better than other reported designs with similar degree of flexibility. Also, the low frequency system clock makes it suitable for low-power applications such as mobile videotelephony.