Motion Estimation Algorithms for Video Compression
Motion Estimation Algorithms for Video Compression
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
VLSI-SOC '01 Proceedings of the IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip: SOC Design Methodologies
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An efficient block-matching criterion for motion estimation and its VLSI implementation
IEEE Transactions on Consumer Electronics
Scalable array architecture design for full search block matching
IEEE Transactions on Circuits and Systems for Video Technology
A novel modular systolic array architecture for full-search block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
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This work describes the VHDL design and implementation of block-based motion estimation in order to make it feasible for real-time video applications. The design was functionally tested and simulated using ModelSim from Mentor Graphics tools, and then verified using both a VHDL testbench and the Matlab® Image processing tools. The design was tested for different image sizes at different clock frequencies with varying block sizes and search areas. With a clock frequency of 400 MHz, the estimated time for motion estimation for QCIF and CIF sequences shows the feasibility for real-time video-codec.