An Efficient VLSI Architecture for Full-Search Block MatchingAlgorithms
Journal of VLSI Signal Processing Systems
Cost Effective VLSI Architectures for Full-SearchBlock-Matching Motion Estimation Algorithm
Journal of VLSI Signal Processing Systems - Special issue on recent development in video: algorithms, implementation and applications
A Systolic Design Methodology with Application toFull-Search Block-Matching Architectures
Journal of VLSI Signal Processing Systems
An Integrated Systolic Array Design for Video Compression
Journal of VLSI Signal Processing Systems
Processor Array Synthesis from Shift-Variant Deep Nested Do Loops
The Journal of Supercomputing
A Memory Efficient Array Architecture for Real-Time Motion Estimation
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
A Parallel Architecture for Stereoscopic Processing
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
A flexible data-interlacing architecture for full-search block-matching algorithm
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Buffer size optimization for full-search block matching algorithms
ASAP '97 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors
Mapping deep nested do-loop DSP algorithms to large scale FPGA array structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results
Journal of VLSI Signal Processing Systems
A hierarchical design methodology for full-search block matching motion estimation
Multidimensional Systems and Signal Processing
Efficient implementation of nested-loop multimedia algorithms
EURASIP Journal on Applied Signal Processing
Hardware Implementation of Block-based Motion Estimation for Real Time Applications
Journal of VLSI Signal Processing Systems
Cronus: A platform for parallel code generation based on computational geometry methods
Journal of Systems and Software
Efficient hierarchical motion estimation algorithm and its VLSI architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VHDL Design for Real Time Motion Estimation Video Applications
Journal of Signal Processing Systems
Analysis and design of a context adaptable SAD/MSE architecture
International Journal of Reconfigurable Computing
Computers and Electrical Engineering
Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC
Journal of Signal Processing Systems
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
Integration, the VLSI Journal
A direct method for optimal VLSI realization of deeply nested n-D loop problems
Microprocessors & Microsystems
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A novel modular systolic array architecture for the full search block matching motion estimation algorithm (FBMA) is presented. The design efforts are focused on matching the array computation to system level input/output constraints. Compared to previously proposed FBMA architectures, this new architecture delivers highest throughput rate, achieves 100% processor utilization, requires much fewer input/output lines (pin count), and is linearly scalable. As such, this architecture offers a feasible solution for progressive-scan HDTV picture format