An Efficient VLSI Architecture for Full-Search Block MatchingAlgorithms

Authors:
Chen-Yi Lee;Mei-Cheng Lu
Affiliations:
Dept. of Electronics Eng. & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan;Dept. of Electronics Eng. & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Venue:
Journal of VLSI Signal Processing Systems
Year:
1997

Citing 2
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Abstract

This paper presents a novel memory-based VLSI architecture for full search block matching algorithms. We propose a semi-systolic array to meet therequirements of high computational complexity, where datacommunications are handled in two styles: (1) global connections forsearch data and (2) local connections for partial sum. Data flow ishandled by a multiple-port memory bank so that all processor elementsfunction on target data items. Thus hardware efficiency achieved can beup to 100%. Both semi-systolic array structure and relatedmemory management strategies for full-search block matching algorithmsare highlighted and discussed in detail in the paper.