Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
VLSI Architecture for Motion Estimation using the Block-Matching Algorithm
EDTC '96 Proceedings of the 1996 European conference on Design and Test
An efficient block-matching criterion for motion estimation and its VLSI implementation
IEEE Transactions on Consumer Electronics
Scalable array architecture design for full search block matching
IEEE Transactions on Circuits and Systems for Video Technology
A novel modular systolic array architecture for full-search block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Hi-index | 0.00 |
The VHDL design code and its implementation using 0.25 μm technology have been demonstrated for the real time video applications. The processing time of a frame running at 400 MHz was estimated to be 8.1 ms for QCIF and CIF Sequences, which accommodates more than 120 frames per second, and this warrant real time video codec. The design was validated and simulated using ModelSim from Mentor Graphics tools, and then verified using both the VHDL testbench and the Matlab® Image processing toolbox. Various alternate search algorithms have been proposed and simulated using Matlab for their real time processing. Skipping "every other column" (SC), and skipping "every other row and column" (SRC) algorithm, "optimal local neighborhood search" (OLNS), and limited-optimal neighborhood search (L-OLNS) have been demonstrated. The microprocessor as a controller is based on RISC processor and it uses pipelining to gain clocking efficiency.