Configuration cloning: exploiting regularity in dynamic DSP architectures
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Energy-efficient motion estimation using error-tolerance
Proceedings of the 2006 international symposium on Low power electronics and design
Hardware Implementation of Block-based Motion Estimation for Real Time Applications
Journal of VLSI Signal Processing Systems
VHDL Design for Real Time Motion Estimation Video Applications
Journal of Signal Processing Systems
Reduced-bit, full search block-matching algorithms and their hardware realizations
ACIVS'05 Proceedings of the 7th international conference on Advanced Concepts for Intelligent Vision Systems
Fuzzy quantization based bit transform for low bit-resolution motion estimation
Image Communication
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The block-matching motion estimation is the most popular technique for motion compensated coding of image sequence. Due to the intensive computational requirement to perform motion estimation (ME) in real-time, application specific VLSI implementation of the ME is indispensable. We present a novel block-matching criterion for motion estimation called reduced bits mean absolute difference (RBMAD). By comparison with conventional schemes, our scheme reduces hardware requirement and increases the speed of computation in VLSI chip with acceptable video performance. We describe in detail the video performances of proposed criterion and conventional ones. We also show our VLSI implementation using the proposed scheme to compare the hardware requirement and operating speed with conventional ones. It is found that RBMAD using 4 bits has reasonable video performance with 57% less VLSI area and 34% faster, thus it is suitable for low cost applications of video coding