An Integrated Systolic Array Design for Video Compression

Authors:
Pol Lin Tai;Chii Tung Liu;Jia Shung Wang
Affiliations:
Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C;Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C;Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan 30043, R.O.C
Venue:
Journal of VLSI Signal Processing Systems
Year:
2002

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Abstract

This paper presents an integrated systolic array design for implementing full-search block matching, 2-D discrete wavelet transform, and full-search vector quantization on the same VLSI architecture. These functions are the prime components in video compression and take a great amount of computation. To meet the real-time application requirements, many systolic array architectures are proposed for individually performing one of those functions. However, these functions contain similar computational procedure. The matrix-vector product forms of the three functions are quite analogous. After extracting the common computation component, we design an integrated one-dimensional systolic array that can perform aforementioned three functions. The proposed architecture can efficiently perform three typical functions: (1) the full-search block matching with block of size 16 × 16 and the search are from −8 to 7; (2) the 2-D 2 level Harr transform with block of size 8 × 8; and (3) the full-search vector quantization with input vector of size 2 × 2. A utilization rate of 100% to 97% is achieved in the course of executing full-search block matching and full-search vector quantization. When it comes to perform 2-D discrete wavelet transform, the utilization rate is about 32%. The proposed integrated architecture has lowered hardware cost and reduced hardware structure. It befits the VLSI implementation for video/image compression applications.