A Quadratic Prediction Based Fractional-Pixel Motion Estimation Algorithm for H.264
ISM '05 Proceedings of the Seventh IEEE International Symposium on Multimedia
Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC
Journal of Signal Processing Systems
Content-Aware Fast Motion Estimation for H.264/AVC
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
A high-performance three-engine architecture for H.264/AVC fractional motion estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV
Journal of Signal Processing Systems
Journal of Signal Processing Systems
Fast sub-pixel motion estimation techniques having lower computational complexity
IEEE Transactions on Consumer Electronics
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
IEEE Transactions on Circuits and Systems for Video Technology
IEEE Transactions on Circuits and Systems for Video Technology
A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation
IEEE Transactions on Circuits and Systems for Video Technology
A novel modular systolic array architecture for full-search block matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
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Fractional Motion Estimation (FME) is an important part of the H.264/AVC video encoding standard. The algorithm can significantly increase the compression ratio of video encoders while improving video quality. However, it is computationally expensive and can consist of over 45% of the total motion estimation runtime. To maximize the performance and utilization of FME implementations on Field-Programmable Gate Arrays (FPGAs), one needs to effectively exploit the inherent parallelism in the algorithm. In this work, we explore two approaches to FME algorithm parallelization in order to effectively increase the processing power of the computing hardware. We call the first method vertical scaling and the second horizontal scaling. We implemented six scaled FME designs on a Xilinx XC5VLX85T (Virtex-5) FPGA. We found that scaling vertically within a 4x4 sub-block is more efficient than scaling horizontally across several sub-blocks. As a result, we were able to achieve higher video resolutions at lower hardware resource cost. In particular, it is shown that the best vertically scaled design can achieve 30fps of QSXGA video with 4 reference frames with only 25.5K LUTS and 28.7K registers.