A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement

Authors:
Marcel Moscarelli Corrêa;Mateus Thurow Schoenknecht;Luciano Volcan Agostini
Affiliations:
Federal University of Pelotas, Pelotas, Brazil;Federal University of Pelotas, Pelotas, Brazil;Federal University of Pelotas, Pelotas, Brazil
Venue:
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Year:
2010

Citing 2
Cited 1

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation

DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools

Analysis and architecture design of scalable fractional motion estimation for H.264 encoding

Integration, the VLSI Journal

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Abstract

This work presents a high performance hardware architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement. This design can process very high definition videos like QHDTV (3840x2048) in real time processing (30 frames per second). It also presents a very optimized arrangement of interpolated samples, which is the main key to achieve an efficient search. The architecture was fully described in VHDL, synthesized to two different Xilinx FPGA devices and achieved the best results when compared to related works.