Data compression: the complete reference
Data compression: the complete reference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Architecture of Full-Search Block Matching for Minimum Memory Bandwidth Requirement
GLS '98 Proceedings of the Great Lakes Symposium on VLSI '98
An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Standard Codecs: Image Compression to Advanced Video Coding
Standard Codecs: Image Compression to Advanced Video Coding
IEEE Transactions on Circuits and Systems for Video Technology
A low-power VLSI architecture for full-search block-matching motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
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HDTV based applications require FSBM to maintain its significantly higher resolution than traditional broadcasting formats (NTSC, SECAM, PAL). This paper proposes some techniques to increase the speed and reduce the area requirements of an FSBM hardware. These techniques are based on modifications of the Sum-of-Absolute-Differences (SAD) computation and the MacroBlock (MB) searching strategy. The design of an FSBM architecture based on the proposed approaches has also been outlined. The highlight of the proposed architecture is its split pipelined design to facilitate parallel processing of macroblocks (MBs) in the initial stages. The proposed hardware has high throughput, low silicon area and compares favorably with other existing FPGA architectures.