A bandwidth-efficient architecture for media processing
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
Improving the performance of speculatively parallel applications on the Hydra CMP
ICS '99 Proceedings of the 13th international conference on Supercomputing
Proceedings of the 27th annual international symposium on Computer architecture
Smart Memories: a modular reconfigurable architecture
Proceedings of the 27th annual international symposium on Computer architecture
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
IEEE Micro
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This paper describes a high bandwidth and low latency hybrid wavepipelined data bus scheme for multi-bank DRAM macros on single chip multiprocessors. Long data bus lines inserted with multiple wave-pipelined stages at each bank input/output are further divided by periodically inserted synchronizing registers to overcome cycle time degradations due to skew and jitter effects in the wave-pipe. Each memory macro controller controls the access sequence not only to avoid internal bank access conflicts, but also to communicate with the other controllers through the hybrid bus. A SPICE simulation result is shown assuming for a 64Mbit macro comparing four 128bit wide data bus schemes. The hybrid scheme can realize over 1GHz on-die data bus for multi-bank DRAM.