High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
A flexible shared-buffer switch for ATM at Gb/s rates
Computer Networks and ISDN Systems
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
IBM Journal of Research and Development
Microarchitecture of a High-Radix Router
Proceedings of the 32nd annual international symposium on Computer Architecture
NetFPGA--An Open Platform for Gigabit-Rate Network Switching and Routing
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
Load balancing and parallelism for the internet
Load balancing and parallelism for the internet
Fulcrum's FocalPoint FM4000: A Scalable, Low-Latency 10GigE Switch for High-Performance Data Centers
HOTI '09 Proceedings of the 2009 17th IEEE Symposium on High Performance Interconnects
Achieving 100% throughput in an input-queued switch
INFOCOM'96 Proceedings of the Fifteenth annual joint conference of the IEEE computer and communications societies conference on The conference on computer communications - Volume 1
The role of optics in future high radix switch design
Proceedings of the 38th annual international symposium on Computer architecture
IEEE Communications Magazine
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Driven by the demand of communication systems, field programmable gate array (FPGA) devices have significantly enhanced their aggregate transceiver bandwidth, reaching terabits per second for the upcoming generation. This paper asks the question whether a single-chip switch fabric can be built that saturates the available transceiver bandwidth. In answering this question, we propose a new switch fabric organization, called Grouped Crosspoint Queued switch, that brings significant memory efficiency over the state-of-the-art organizations. This makes it possible to build high bandwidth, high radix switches directly on FPGA that rivals ASIC performance. The proposal was validated at small scale by a 16x16 160Gps switch on the available Virtex-6 device, and simulated at a larger scale of fat-tree switching network with 5Tbps capacity.