NetFPGA: reusable router architecture for experimental research
Proceedings of the ACM workshop on Programmable routers for extensible services of tomorrow
A scalable, commodity data center network architecture
Proceedings of the ACM SIGCOMM 2008 conference on Data communication
On runtime management in multi-core packet processing systems
Proceedings of the 4th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
PortLand: a scalable fault-tolerant layer 2 data center network fabric
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
SmartRE: an architecture for coordinated network-wide redundancy elimination
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
LIPSIN: line speed publish/subscribe inter-networking
Proceedings of the ACM SIGCOMM 2009 conference on Data communication
Design of a network service processing platform for data path customization
Proceedings of the 2nd ACM SIGCOMM workshop on Programmable routers for extensible services of tomorrow
Building a fast, virtualized data plane with programmable hardware
Proceedings of the 1st ACM workshop on Virtualized infrastructure systems and architectures
Building a fast, virtualized data plane with programmable hardware
ACM SIGCOMM Computer Communication Review
Leaping multiple headers in a single bound: wire-speed parsing using the kangaroo system
INFOCOM'10 Proceedings of the 29th conference on Information communications
Accelerated virtual switching with programmable NICs for scalable data center networking
Proceedings of the second ACM SIGCOMM workshop on Virtualized infrastructure systems and architectures
Hedera: dynamic flow scheduling for data center networks
NSDI'10 Proceedings of the 7th USENIX conference on Networked systems design and implementation
Fair multithreading on packet processors for scalable network virtualization
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Design of a secure packet processor
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Axon: a flexible substrate for source-routed ethernet
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
The case for hardware transactional memory in software packet processing
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Exact temporal characterization of 10 Gbps optical wide-area network
IMC '10 Proceedings of the 10th ACM SIGCOMM conference on Internet measurement
Simplifying data path processing in next-generation routers
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Experience with high-speed automated application-identification for network-management
Proceedings of the 5th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Efficient event processing through reconfigurable hardware for algorithmic trading
Proceedings of the VLDB Endowment
Can the production network be the testbed?
OSDI'10 Proceedings of the 9th USENIX conference on Operating systems design and implementation
NetTM: faster and easier synchronization for soft multicores via transactional memory
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
An accelerated and energy-efficient traffic monitor using the NetFPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Towards highly parallel event processing through reconfigurable hardware
Proceedings of the Seventh International Workshop on Data Management on New Hardware
Application-specific signatures for transactional memory in soft processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Using NetMagic to observe fine-grained per-flow latency measurements
Proceedings of the ACM SIGCOMM 2011 conference
ALIAS: scalable, decentralized label assignment for data centers
Proceedings of the 2nd ACM Symposium on Cloud Computing
Leveraging Zipf's law for traffic offloading
ACM SIGCOMM Computer Communication Review
Application-specific signatures for transactional memory in soft processors
ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications
Saturating the transceiver bandwidth: switch fabric design on FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Compiling high throughput network processors
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A dynamically reconfigured multi-FPGA network platform for high-speed malware collection
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
uvNIC: rapid prototyping network interface controller device drivers
Proceedings of the ACM SIGCOMM 2012 conference on Applications, technologies, architectures, and protocols for computer communication
USENIX ATC'12 Proceedings of the 2012 USENIX conference on Annual Technical Conference
Netmap: a novel framework for fast packet I/O
USENIX ATC'12 Proceedings of the 2012 USENIX conference on Annual Technical Conference
The power of batching in the Click modular router
Proceedings of the Asia-Pacific Workshop on Systems
uvNIC: rapid prototyping network interface controller device drivers
ACM SIGCOMM Computer Communication Review - Special october issue SIGCOMM '12
Deep packet inspection tools and techniques in commodity platforms: Challenges and trends
Journal of Network and Computer Applications
The power of batching in the click modular router
APSys'12 Proceedings of the Third ACM SIGOPS Asia-Pacific conference on Systems
Mobile cloud computing: A survey
Future Generation Computer Systems
NetSlices: scalable multi-core packet processing in user-space
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
Malacoda: towards high-level compilation of network security applications on reconfigurable hardware
Proceedings of the eighth ACM/IEEE symposium on Architectures for networking and communications systems
NetStage/DPR: A self-reconfiguring platform for active and passive network security operations
Microprocessors & Microsystems
Confused, timid, and unstable: picking a video streaming rate is hard
Proceedings of the 2012 ACM conference on Internet measurement conference
Reproducible network experiments using container-based emulation
Proceedings of the 8th international conference on Emerging networking experiments and technologies
Towards secure mobile cloud computing: A survey
Future Generation Computer Systems
Computers and Electrical Engineering
From 1G to 10G: code reuse in action
Proceedings of the first edition workshop on High performance and programmable networking
SoNIC: precise realtime software access and control of wired networks
nsdi'13 Proceedings of the 10th USENIX conference on Networked Systems Design and Implementation
An on-demand queue management architecture for a programmable traffic manager
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Online NetFPGA decision tree statistical traffic classifier
Computer Communications
High-performance implementation of in-network traffic pacing for small-buffer networks
Computer Communications
No silver bullet: extending SDN to the data plane
Proceedings of the Twelfth ACM Workshop on Hot Topics in Networks
Queue - Large-Scale Implementations
SENIC: scalable NIC for end-host rate limiting
NSDI'14 Proceedings of the 11th USENIX Conference on Networked Systems Design and Implementation
Hi-index | 0.00 |
The NetFPGA platform enables students and researchers to build high-performance networking systems in hardware. A new version of the NetFPGA platform has been developed and is available for use by the academic community. The NetFPGA 2.1 platform now has interfaces that can be parameterized, therefore enabling development of modular hardware designs with varied word sizes. It also includes more logic and faster memory than the previous platform. Field Programmable Gate Array (FPGA) logic is used to implement the core data processing functions while software running on embedded cores within the FPGA and/or programs running on an attached host computer implement only control functions. Reference designs and component libraries have been developed for the CS344 course at Stanford University. Open-source Verilog code is available for download from the project website.