DFT/FFT and Convolution Algorithms: Theory and Implementation
DFT/FFT and Convolution Algorithms: Theory and Implementation
Low-rate TCP-targeted denial of service attacks: the shrew vs. the mice and elephants
Proceedings of the 2003 conference on Applications, technologies, architectures, and protocols for computer communications
Collaborative Change Detection of DDoS Attacks on Community and ISP Networks
CTS '06 Proceedings of the International Symposium on Collaborative Technologies and Systems
NetFPGA--An Open Platform for Gigabit-Rate Network Switching and Routing
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
On the relationship between capacity and distance in an underwater acoustic communication channel
ACM SIGMOBILE Mobile Computing and Communications Review
A Novel Embedded Accelerator for Online Detection of Shrew DDoS Attacks
NAS '08 Proceedings of the 2008 International Conference on Networking, Architecture, and Storage
Remote detection of bottleneck links using spectral and statistical methods
Computer Networks: The International Journal of Computer and Telecommunications Networking
Modeling and Detection of Camouflaging Worm
IEEE Transactions on Dependable and Secure Computing
Normalization of the Speech Modulation Spectra for Robust Speech Recognition
IEEE Transactions on Audio, Speech, and Language Processing
Direction-Adaptive Discrete Wavelet Transform for Image Compression
IEEE Transactions on Image Processing
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The shrew DDoS attacks are stealth low-rate TCP-targeted DDoS attacks, which conceal their malicious activities into normal traffic. Although the good pretense eludes them from being detected in time domain, the existent energy exposes them in frequency domain. Online Power Spectral Density (PSD) analysis necessitates real-time PSD data conversion is a must. In this paper, an optimized FPGA based real-time PSD converter is proposed, which is based on our innovative component-reusable Auto-Correlation (AC) algorithm and the adapted 2N-point real-valued Discrete Fourier Transform (DFT) algorithm. Further optimization is achieved through the exploration of algorithm characters and hardware parallelism for this case. The evaluation results from both simulation and synthesis are provided. The conversion of a 512-point data sequence can be finished in the time interval of sampling one data point; and the overall design could be easily fitted in a Xilinx Virtex2 Pro FGPA.