Congestion avoidance and control
SIGCOMM '88 Symposium proceedings on Communications architectures and protocols
Optical burst switching (OBS) - a new paradigm for an optical Internet
Journal of High Speed Networks - Special issue on optical networking
Proceedings of the 2004 conference on Applications, technologies, architectures, and protocols for computer communications
Part III: routers with very small buffers
ACM SIGCOMM Computer Communication Review
Open issues in router buffer sizing
ACM SIGCOMM Computer Communication Review
NetFPGA--An Open Platform for Gigabit-Rate Network Switching and Routing
MSE '07 Proceedings of the 2007 IEEE International Conference on Microelectronic Systems Education
Simulation studies on router buffer sizing for short-lived and pacing TCP flows
Computer Communications
Perspectives on router buffer sizing: recent results and open problems
ACM SIGCOMM Computer Communication Review
Packet pacing in small buffer optical packet switched networks
IEEE/ACM Transactions on Networking (TON)
Practical packet pacing in small-buffer networks
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
A practical on-line pacing scheme at edges of small buffer networks
INFOCOM'10 Proceedings of the 29th conference on Information communications
Approaches to optical Internet packet switching
IEEE Communications Magazine
Optical burst switching: a viable solution for terabit IP backbone
IEEE Network: The Magazine of Global Internetworking
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Demands on data communication networks continue to drive the need for increasingly faster link speeds. Optical packet switching networks promise to provide data rates that are sufficiently high to satisfy the needs of the future Internet core network. However, a key technological problem with optical packet switching is the very small size of packet buffers that can be implemented in the optical domain. Existing protocols, for example the widely used Transmission Control Protocol (TCP), do not perform well in such small-buffer networks. To address this problem, we have proposed techniques for actively pacing traffic at edge networks to ensure that traffic bursts are reduced or eliminated and thus do not cause packet losses in routers with small buffers. We have also shown that this traffic pacing can improve the performance of conventional networks that use small buffers (e.g., to reduce the cost of buffer memory on routers). A key challenge in this context is to develop systems that can perform such packet pacing efficiently and at high data rates. In this paper, we present the design and prototype of a hardware implementation of our packet pacing technique. We discuss and evaluate design trade-offs and present performance results from an prototype implementation based on a NetFPGA fieldprogrammable gate array system. Our results show that traffic pacing can be implemented with few hardware resources and without reducing system throughput. Therefore, we believe that traffic pacing can be deployed widely to improve the operation of current and future networks.