High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Improving the performance of input-queued ATM packet switches
IEEE INFOCOM '92 Proceedings of the eleventh annual joint conference of the IEEE computer and communications societies on One world through communications (Vol. 1)
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
Characterization of the Burst Stabilization Protocol for the RR/RR CICQ Switch
LCN '03 Proceedings of the 28th Annual IEEE International Conference on Local Computer Networks
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In this paper a high performance and simple scheduling algorithm for combined input-crosspoint crossbar switches, called exhaustive round-robin (ERR), is presented and analyzed. We propose using of this scheduling system for arbitration at inputs and crosspoints. If the virtual output queue (crosspoint buffer) becomes empty, the input (crosspoint) arbiter updates its pointer to the next location in a fixed order. Otherwise, the pointer remains at the current virtual output queue (crosspoint buffer). It is shown that this new solution achieves 100% throughput for several admissible traffic patterns, including uniform and unbalanced traffic, using only one-cell crosspoint buffers. ERR-ERR ensures service to the queues with high load using the exhaustive service and to the queues with low load using RR selection. Also, the performance of proposed CICQ under unbalanced traffic pattern increases and converges to output buffered switch performance as the crosspoint buffer increases. This scheduling algorithm is based only on the information about cell existing in virtual output queue (crosspoint buffer). Therefore, it requires much less hardware than the proposed algorithms. These results show the advantage of the ERR-ERR CICQ switch as a competitor for the next generation of high-performance packet switches.