High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
A novel approach to queue stability analysis of polling models
Performance Evaluation - Special issue on performance and control of network systems
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Analytical router modeling for networks-on-chip performance analysis
Proceedings of the conference on Design, automation and test in Europe
Matching output queueing with a combined input/output-queued switch
IEEE Journal on Selected Areas in Communications
Delay analysis of wormhole based heterogeneous NoC
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A two-class continuous-time queueing model with dedicated servers and global FCFS service discipline
ASMTA'11 Proceedings of the 18th international conference on Analytical and stochastic modeling techniques and applications
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Packet switches have been studied extensively as part of ATM and LAN networks under the assumption that the number of input ports N tends to infinity. Our study of packet switches is motivated by networks on chips, where N is usually 4 or 5 and asymptotic models lead to inaccurate results. We consider small non-uniform switches and accurately approximate stability conditions and throughput. In addition to this, we approximate the mean waiting time in the switch by that in a ./Geo/1 queue.