High-performance multi-queue buffers for VLSI communications switches
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Design and analysis of buffered crossbars and banyans with cut-through switching
Proceedings of the 1990 ACM/IEEE conference on Supercomputing
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
WSC '96 Proceedings of the 28th conference on Winter simulation
The iSLIP scheduling algorithm for input-queued switches
IEEE/ACM Transactions on Networking (TON)
Round-robin arbiter design and generation
Proceedings of the 15th international symposium on System Synthesis
Packet-mode scheduling in input-queued cell-based switches
IEEE/ACM Transactions on Networking (TON)
Design of a High-Speed Overlapped Round Robin (ORR) Arbiter
LCN '03 Proceedings of the 28th Annual IEEE International Conference on Local Computer Networks
Input queued switches for variable length packets: analysis for Poisson and self-similar traffic
Computer Communications
Saturn: a terabit packet switch using dual round robin
IEEE Communications Magazine
IEEE Journal on Selected Areas in Communications
Integrated Services Packet Network Using Bus Matrix Switch
IEEE Journal on Selected Areas in Communications
An evolution to crossbar switches with virtual output queuing and buffered cross points
IEEE Network: The Magazine of Global Internetworking
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Increasing link speeds and port counts in packet switches demand that methods for minimizing internal speed-up and implementing fast scheduling be developed. Combined input and cross point queued (CICQ) switches with round-robin (RR) polling of virtual output queues (VOQ) and of cross point buffers can natively forward variable-length packets without a required internal segmentation into cells. However, native switching of variable-length packets results in unfairness between ports. To eliminate this unfairness, we propose a block transfer mechanism that transfers up to a predefined number of bytes of packet data from a selected VOQ. This mechanism does not require internal speed-up. We also propose an overlapped RR (ORR) arbiter design that fully overlaps RR polling and scheduling. Using simulation and both synthetic and traced packet traffic as input, we show that the RR/RR CICQ switch with the block transfer mechanism has a lower delay than an input queued (IQ) switch that internally uses cells. We also show that the ORR arbiter is scalable, work conserving, and fair.