Gauss: a simple high performance switch architecture for ATM
SIGCOMM '90 Proceedings of the ACM symposium on Communications architectures & protocols
Performance evaluation of new scheduling methods for the RR/RR CICQ switch
Computer Communications
Proposed high speed packet switch for broadband integrated networks
Computer Communications
Research: Analysis and design of Banyan and crossbar switches with bypass queues
Computer Communications
Research: Performance of ATM switch fabric using cross-point buffers
Computer Communications
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For several years, Fujitsu has been researching and developing high-speed packet switching networks, the result being an integrated multimedia information networks architecture. This architecture has already been applied to LAN systems and can now be applied to wide area corporate networks thanks to the new developments described in this paper. The most important technology-the bus matrix switch-provides a quantum leap in processing capacity up to several Gbit/s (few millions of packets every second), while keeping a very low switching delay. The performance evaluation based on our prototype models is also considered in detail. For example, a voice delay of less than 20 ms is obtained for five-hop communication. The new technologies will greatly improve for computer networks and will also enable basic and broadband ISDN.