Proposed high speed packet switch for broadband integrated networks

Authors:
Krishna Thilakam;Ashok Jhunjhunwala
Affiliations:
CAD/VLSI Group, MC Division, Indian Telephone Industries, Banglore 560016, India;Department of Electrical Engineering, Indian Institute of Technology, Madras 600036, India
Venue:
Computer Communications
Year:
1989

Citing 4
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Abstract

The design of a high speed, broadband packet switch with two priority levels for application in integrated voice/data networks is presented. The packet switch can efficiently cope with 128 byte packets converging on it from eight 140 Mbit/s dynamic time division multiplexed fibre optic links. The packet switch throughput varies with the load and traffic composition, and the delay experienced by voice and data packets is within 300 @ms and 3 ms, respectively. The design is implemented by task-sharing in a multi-processor configuration. The design of the packet switch, including its subsystems, is detailed here.