Inside Parallel Computers: Trends in Interconnection Networks

• Authors: Howard Jay Siegel;Craig B. Stunkel
• Venue: IEEE Computational Science & Engineering
• Year: 1996

Computational scientists who depend on parallel computing to let them run larger models in less time will be disappointed unless the processors can pass information back and forth quickly. The interconnection networks through which processors communicate in tightly coupled parallel machines thus remain a vital research topic for computer architects. Over the last two decades the demands placed on these networks have evolved. Early SIMD machines required the simultaneous transfer of data from each network input to each output for a relatively small set of communication configurations; whereas the SIMD and MIMD machines of today need to support varied patterns of synchronous and asynchronous traffic, respectively. Interconnection networks can be categorized according to criteria such as topology, routing strategy, and switching technique. They vary widely in cost, fault tolerance, simplicity, amenability to partitioning, and aggregate bandwidth for local and nonlocal traffic patterns. No clear consensus exists on optimal topologies. However, meshes, hypercubes, MINs, and BMINs have been the most widely used recently. Circuit-switching and store-and-forward switching have yielded to wormhole routing, and it is possible that, as improvements in VLSI increase the buffer capacity per switch, virtual cut-through or hybrid wormhole-VCT solutions will dominate in the future. Likewise, these VLSI improvements will favor the increasing use of multiple switch input queues or central buffering to attack head-of-the-line blocking. Other developments to watch include the influence of ATM architecture and technology, the emergence of low-cost optical interconnections, and optical switching. Corresponding author: Howard Jay Siegel, School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47907-1285. E-mail: [e-mail]