Symmetric Crossbar Arbiters for VLSI Communication Switches
IEEE Transactions on Parallel and Distributed Systems
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
Destination-Based HoL Blocking Elimination
ICPADS '06 Proceedings of the 12th International Conference on Parallel and Distributed Systems - Volume 1
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
ICPP '07 Proceedings of the 2007 International Conference on Parallel Processing
Low-latency scheduling in large switches
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
High-radix crossbar switches enabled by proximity communication
Proceedings of the 2008 ACM/IEEE conference on Supercomputing
Backlog aware scheduling for ingress memories in high-radix, single-stage switches
GLOBECOM'09 Proceedings of the 28th IEEE conference on Global telecommunications
BBQ: a straightforward queuing scheme to reduce hol-blocking in high-performance hybrid networks
Euro-Par'13 Proceedings of the 19th international conference on Parallel Processing
A new proposal to deal with congestion in InfiniBand-based fat-trees
Journal of Parallel and Distributed Computing
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To avoid head of line blocking in switches, Virtual Output Queues (VOQs) are commonly used. However, the number of VOQs grows quadratically with the number of ports, making this approach impractical for large switches. In this paper, we propose Dynamic Switch Buffer Management (DSBM) to tackle this problem. Similar to DBBM [3], it saves memory by reducing the number of buffers. Our scheme significantly improves the performance by dynamically assigning the incoming cells to the least occupied buffers.