Dynamically-Allocated Multi-Queue Buffers for VLSI Communication Switches
IEEE Transactions on Computers
High-speed switch scheduling for local-area networks
ACM Transactions on Computer Systems (TOCS)
IEEE Transactions on Parallel and Distributed Systems
Credit-Flow-Controlled ATM for MP Interconnection: The ATLAS I Single-Chip ATM Switch
HPCA '98 Proceedings of the 4th International Symposium on High-Performance Computer Architecture
Flattened butterfly: a cost-efficient topology for high-radix networks
Proceedings of the 34th annual international symposium on Computer architecture
Technology-Driven, Highly-Scalable Dragonfly Topology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Optimized InfiniBandTM fat-tree routing for shift all-to-all communication patterns
Concurrency and Computation: Practice & Experience - International Supercomputing Conference (ISC07)
Buffer Management Strategies to Reduce HoL Blocking
IEEE Transactions on Parallel and Distributed Systems
Scalable alternatives to virtual output queuing
ICC'09 Proceedings of the 2009 IEEE international conference on Communications
OBQA: Smart and cost-efficient queue scheme for Head-of-Line blocking elimination in fat-trees
Journal of Parallel and Distributed Computing
vFtree - A Fat-Tree Routing Algorithm Using Virtual Lanes to Alleviate Congestion
IPDPS '11 Proceedings of the 2011 IEEE International Parallel & Distributed Processing Symposium
Cost-effective queue schemes for reducing head-of-line blocking in fat-trees
Concurrency and Computation: Practice & Experience
Proceedings of the first international workshop on Network-aware data management
Dynamic evolution of congestion trees: analysis and impact on switch architecture
HiPEAC'05 Proceedings of the First international conference on High Performance Embedded Architectures and Compilers
A New Family of Hybrid Topologies for Large-Scale Interconnection Networks
NCA '12 Proceedings of the 2012 IEEE 11th International Symposium on Network Computing and Applications
Towards Modeling Interconnection Networks of Exascale Systems with OMNet++
PDP '13 Proceedings of the 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing
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Head-of-Line (HoL) blocking is a well-known phenomenon that may dramatically degrade the performance of the modern high-performance interconnection networks. Many techniques have been proposed to solve this problem, most of them based on separating traffic flows into different queues at switch ports. However, the efficiency of these proposals may vary depending on the network topology or routing algorithm, as many of them are not aware of any specific network configuration. By contrast, other schemes are tailored to specific topologies like fat-trees, achieving a greater efficiency than "topology-agnostic" schemes. In this paper we propose a straightforward queuing scheme intended to be used in an efficient, recently-proposed hybrid topology. Our proposal significantly boosts network performance with respect to other queuing schemes while requiring similar or fewer resources. Moreover, the implementation of this scheme in InfiniBand-based networks is elementary thanks to the mapping of Service-Levels to Virtual-Lanes supported by this specification.