Low-latency scheduling in large switches

Authors:
Wladek Olesinski;Nils Gura;Hans Eberle;Andres Mejia
Affiliations:
Sun Microsystems Laboratories, Menlo Park, CA;Sun Microsystems Laboratories, Menlo Park, CA;Sun Microsystems Laboratories, Menlo Park, CA;Universidad Politecnica de Valencia, Valencia, Spain
Venue:
Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems
Year:
2007

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Abstract

Scheduling in large switches is challenging. Arbiters must operate at high rates to keep up with the high switching rates demanded by multi-gigabit-per-second link rates and short cells. Low-latency requirements of some applications also challenge the design of schedulers. In this paper, we propose the Parallel Wrapped Wave Front Arbiter with Fast Scheduler (PWWFA-FS). We analyze its performance, present simulation results, discuss its implementation, and show how this scheme can provide low latency under light load while scaling to large switches with multi-terabit-per-second throughput and hundreds of ports.