Design of the switching controller for the high-capacity non-blocking internet router

Authors:
Miloš Petrovic;Aleksandra Smiljanic;Miloš Blagojevic
Affiliations:
School of Electrical Engineering, Belgrade University, Belgrade, Serbia;School of Electrical Engineering, Belgrade University, Belgrade, Serbia and Polytechnic Institute of NYU, Brooklyn, NY;School of Electrical Engineering, Belgrade University, Belgrade, Serbia
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2009

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Abstract

The sequential greedy scheduling (SGS) algorithm is a scalable maximal matching algorithm. This algorithm was conceptually proposed and well received since it provides non-blocking in an Internet router with input buffers and a cross-bar, unlike other existing implementations. In this paper, we implent a new design of the SGS algorithm, and determine its exact behaviour, performance and QoS that it provides. We examine different design options and measure the performance of their implementations in terms of their scalability and speed. It will be shown that multiple scheduler modules of a terabit Internet router can be implemented on a low-cost field-programmable gate-array (FPGA) device, and that the processing can be performed within the desired time slot duration. Proper functioning of the implemented scheduler was confirmed through thorough software and hardware testing.