Performance and complexity analysis of credit-based end-to-end flow control in network-on-chip

Authors:
Seongmin Noh;Daehyun Kim;Vu-Duc Ngo;Hae-Wook Choi
Affiliations:
System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University, Taejon, Korea;System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University, Taejon, Korea;System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University, Taejon, Korea;System VLSI Lab, SITI Research Center, School of Engineering, Information and Communications University, Taejon, Korea
Venue:
ISPA'07 Proceedings of the 5th international conference on Parallel and Distributed Processing and Applications
Year:
2007

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Abstract

Network-on-Chip is an alternative paradigm to improve communication bandwidth compared to bus-based communication, and its performance degrades if there is no effective flow control method., Heterogeneous networks with very slow processing elements (PEs) especially need a flow control mechanism at the transport layer to prevent too much packet injection. In this paper, a credit-based end-to-end flow control (CB-EEFC) is implemented to control the network latency at high traffic loads. Simulation in mesh networks shows improved performance in latency and 0.5% up to 3% saturated throughput decrease with the CB-EEFC method. RTL gate level simulation shows that a network interface using CB-EEFC brings about a 31.4% increase in complexity compared to a network interface without CB-EEFC.