Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
Journal of the ACM (JACM)
Planar-adaptive routing: low-cost adaptive networks for multiprocessors
Journal of the ACM (JACM)
A Traffic-Balanced Adaptive Wormhole Routing Scheme for Two-Dimensional Meshes
IEEE Transactions on Computers
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Principles and Practices of Interconnection Networks
Principles and Practices of Interconnection Networks
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
NoC Design and Implementation in 65nm Technology
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
IEEE Transactions on Computers
Application Specific Routing Algorithms for Networks on Chip
IEEE Transactions on Parallel and Distributed Systems
An Advanced NoP Selection Strategy for Odd-Even Routing Algorithm in Network-on-Chip
ICA3PP '09 Proceedings of the 9th International Conference on Algorithms and Architectures for Parallel Processing
SAMOS'06 Proceedings of the 6th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
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In this paper, we propose a methodology to design routing algorithms for Network-on-Chip (NoC) which are customized for a set of applications The routing algorithms are achieved by breaking all the cycles in the application specific channel dependency graph(ASCDG) Thus, the result routing algorithms are ensured to be deadlock-free The proposed method can overcome the shortcomings of the method in [1] which heavily depends on the order of the cycles being treated and has high computational complexity Simulation results show that the Routing Algorithms by Breaking Cycles (RABC) improves the performance significantly.