Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Proceedings of Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and Design Tools and Architectures for Multicore Embedded Computing Platforms
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The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These models need to be functional and timing accurate in order to address different design use-cases during the SoC development. However the typical issue with Transaction Level Modeling (TLM) techniques is the accuracy vs. simulation speed trade-off. Models that can run at high simulation speeds are often modeled at abstraction levels that make them unsuitable for use-cases where timing accuracy is required. Similarly, most models that are cycle accurate are inherently too slow (due to clock sensitive processes) to be used in use-cases where high simulation speed is key. This paper introduces a new methodology that enables the creation of fast and cycle accurate protocol specific bus-based communication models, based on the new TLM 2.0 standard from the Open SystemC Initiative (OSCI).