Dynamic communication models in embedded system co-simulation
DAC '97 Proceedings of the 34th annual Design Automation Conference
A geographically distributed framework for embedded system design and validation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Multilanguage design of heterogeneous systems
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Cycle and phase accurate DSP modeling and integration for HW/SW co-verification
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Virtual synchronization for fast distributed cosimulation of dataflow task graphs
Proceedings of the 15th international symposium on System Synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
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Increasing time to market pressures, greater design complexity and increasing software content are driving systems designers to look towards new ways of performing system validation. Hardware and software design teams are using separate tools to develop different components that will work closely together in a system. Combining these design environments holds the promise of finding problems earlier in the design cycle. The key to a successful integration of these technologies is to provide sufficient performance to run reasonable amounts of software. This paper describes a system which integrates an event driven hardware simulator with an instruction set simulator. This system allows dynamic partitioning of the code and data space between the hardware and software simulators. This capability provides performance sufficient for running software without sacrificing the accuracy required by the hardware simulator.