A systematic IP and bus subsystem modeling for platform-based system design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Requirements for Interfacing IP-Components in Re-configurable Platforms
Journal of VLSI Signal Processing Systems
Double profiling methodology for video processing platform
AIC'04 Proceedings of the 4th WSEAS International Conference on Applied Informatics and Communications
Observability Checking to Enhance Diagnosis of Real Time Electronic Systems
DS-RT '08 Proceedings of the 2008 12th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications
SystemC-based HW/SW co-simulation platform for system-on-chip (SoC) design space exploration
International Journal of Information and Communication Technology
HIFsuite: tools for HDL code conversion and manipulation
EURASIP Journal on Embedded Systems
Co-simulation framework of SystemC SoC virtual prototype and custom logic (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Embedded systems design requires the development of complex HW modules to cope with the most stringent timing constraints of the specifications. This implies the need to update and enrich HW design methodologies to face abstraction and novel requirements. Here we will present some results of design practice of HW modules in this context. Co-simulation and synthesis are combined in this approach to achieve higher abstraction levels in the design, to improve validation and re-use of previous designs and human experience. The proposed methodology is embedded in a SystemC based design flow. The SystemC-VHDL co-simulator tool is also based on a SystemC/C++ front-end developed to support the co-simulation between VHDL and SystemC. The prototypal state of the adopted tools increase the novelty and interest of the approach.