Automatic array privatization and demand-driven symbolic analysis
Automatic array privatization and demand-driven symbolic analysis
Advanced compiler design and implementation
Advanced compiler design and implementation
Automatic parallelization of divide and conquer algorithms
Proceedings of the seventh ACM SIGPLAN symposium on Principles and practice of parallel programming
Software environment for a multiprocessor DSP
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip communication architecture for OC-768 network processors
Proceedings of the 38th annual Design Automation Conference
Parallel Programming with Polaris
Computer
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
A Layered, Codesign Virtual Machine Approach to Modeling Computer Systems
Proceedings of the conference on Design, automation and test in Europe
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduler implementation in MP SoC design
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Power optimizations for the MLCA using dynamic voltage scaling
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Amdahl's law revisited for single chip systems
International Journal of Parallel Programming
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
Automatic task generation for the multi-level computing architecture
PDCS '07 Proceedings of the 19th IASTED International Conference on Parallel and Distributed Computing and Systems
Task superscalar: using processors as functional units
HotPar'10 Proceedings of the 2nd USENIX conference on Hot topics in parallelism
MP-Tomasulo: A Dependency-Aware Automatic Parallel Execution Engine for Sequential Programs
ACM Transactions on Architecture and Code Optimization (TACO)
Parallelization of multimedia applications on the multi-level computing architecture
Journal of Embedded Computing
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This template architecture for SoC systems uses superscalar techniques to exploit task-level parallelism among different processing units. It supports a natural programming model that relieves programmers from explicitly synchronizing tasks and communicating data. Code transformations that improve application performance are easy to incorporate in compilers for this architecture.