An updated survey of GA-based multiobjective optimization techniques
ACM Computing Surveys (CSUR)
System-on-a-chip verification: methodology and techniques
System-on-a-chip verification: methodology and techniques
Parallel Computer Architecture: A Hardware/Software Approach
Parallel Computer Architecture: A Hardware/Software Approach
Evolutionary Algorithms for Solving Multi-Objective Problems
Evolutionary Algorithms for Solving Multi-Objective Problems
Rapid Hardware Prototyping on RPM-2
IEEE Design & Test
Parallel simulation of chip-multiprocessor architectures
ACM Transactions on Modeling and Computer Simulation (TOMACS)
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC
Proceedings of the conference on Design, automation and test in Europe - Volume 1
High-level modeling and simulation of single-chip programmable heterogeneous multiprocessors
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
Reducing the run-time complexity of multiobjective EAs: The NSGA-II and other algorithms
IEEE Transactions on Evolutionary Computation
Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Prohibitive simulation time of single multiprocessor configuration makes large design space exploration impossible without massive use of computing resources and still implementation issues are not tackled. This paper proposes a new performance evaluation methodology for multiprocessors on chip which conduct a multiobjective design space exploration through emulation. The proposed approach is validated on a 4 way multiprocessor on chip design space exploration where a 6 order of magnitude improvement have been achieved over cycle accurate simulation.