Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation

• Authors: Xinyu Li;Omar Hammami
• Venue: Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
• Year: 2009

Future generation multiprocessor system on chip (MPSOC) will be based on hundreds of processors connected through network on chips. One of the challenges is to tackle the design productivity required to reach this goal. We propose a NOC based small scale multiprocessor IP (SSM IP) as a building block for large scale multiprocessor. The architecture of the small scale multiprocessor is based on a 2x2 mesh with 3 Xilinx Microblaze processors and 2 SRAM on chip memories per switch. The network on chip topology is mesh for its scalability properties and easy extensibility. A clustered design has been preferred over a full mesh in order to fully exploit the data locality processing of image and multimedia applications. The implementation of the small scale multiprocessor has been realized by targeting the largest Xilinx Virtex-4 FPGA chip the FX140. Design has been realized using the Xilinx tools (EDK, ISE) with the Xilinx library of IPs. The objective of the implementation was to design a multiprocessor of sufficient scale to be significant while leaving some chip area and resources for design space exploration. Images can be distributed equally among the shared memories of each cluster so that processors belonging to a cluster can operate on the image portion associated to a cluster. Architectural variations among 4 selected architectures demonstrate the area saving and performance potential of soft IP. In addition reasonable synthesis, place and route execution time and achieved target frequencies justify the design effort.