Schedule validation for embedded reactive real-time systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment
Journal of the ACM (JACM)
Symbolic Model Checking
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
VIS: A System for Verification and Synthesis
CAV '96 Proceedings of the 8th International Conference on Computer Aided Verification
Automatic test bench generation for simulation-based validation
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Efficient methods for embedded system design space exploration
Proceedings of the 37th Annual Design Automation Conference
Early Power Estimation for System-on-Chip Designs
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
System-Level Test Bench Generation in a Co-Design Framework
ETW '00 Proceedings of the IEEE European Test Workshop
A Constructive Approach to Hardware/Software Partitioning
Formal Methods in System Design
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This paper presents a new protocol for parallel and distributed simulation of VLSI systems. It is novel in two aspects: first, it combines optimistic and conservative synchronization methods, allowing processes to self-adapt for maximal utilization of concurrency. Second, it does not require any application-dependent information like lookahead, which in many cases is unknown, zero, or difficult to automatically obtain from a design in a hardware description language. All these features make it very convenient and practical, extending the class of applications to at least all VHDL circuits, including delta cycle. The proposed protocol has been implemented and used for VHDL simulation. Experimental results on several large VHDL circuits (between 1411 and 14704 processes) have shown promising linear speedups. We also observed that the dynamic synchronization, in which processes automatically adapt to optimistic or conservative behavior, follows closely or finds a very good configuration. This protocol may have a string impact for mixed-signal circuit simulation, where digital parts may be optimistic and heavy-state analog parts, conservative.