A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hardware-Software Cosynthesis for Digital Systems
IEEE Design & Test
Dynamic hardware/software partitioning: a first approach
Proceedings of the 40th annual Design Automation Conference
Run-time modeling and estimation of operating system power consumption
SIGMETRICS '03 Proceedings of the 2003 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
Hardware Software Partitioning Using Genetic Algorithm
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
A Petri Net Based Approach for Hardware/Software Partitioning
Proceedings of the 14th symposium on Integrated circuits and systems design
Embedded Software for Soc
Timed RTOS Modeling for Embedded System Design
RTAS '05 Proceedings of the 11th IEEE Real Time on Embedded Technology and Applications Symposium
Energy macromodeling of embedded operating systems
ACM Transactions on Embedded Computing Systems (TECS)
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The RTOS (Real-Time Operating System) is a critical component in the SoC (System-on-a-Chip), which consumes the dominant part of total system energy. A RTOS system-level power optimization approach based on hardwaresoftware partitioning (RTOS-Power partitioning) can significantly minimize the energy consumption of a SoC. This paper presents a new model for RTOSPower partitioning, which helps in understanding the essence of the RTOSPower partitioning techniques. A discrete Hopfield neural network approach for implementing the RTOS-Power partitioning is proposed, where a novel energy function, operating equation and coefficients of the neural network are redefined. Simulations are carried out with comparison to other optimization techniques. Experimental results demonstrate that the proposed method can achieve higher energy savings up to 60% at relatively low costs.