PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
A DAG-based design approach for reconfigurable VLIW processors
DATE '99 Proceedings of the conference on Design, automation and test in Europe
A C compiler for a processor with a reconfigurable functional unit
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Proceedings of the 27th annual international symposium on Computer architecture
IEEE Transactions on Computers
Coarse grain reconfigurable architecture (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Media Processing Applications on the Imagine Stream Processor
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Pipelined Fast 2-D DCT Architecture for JPEG Image Compression
Proceedings of the 14th symposium on Integrated circuits and systems design
Parallel Processing Architectures for Reconfigurable Systems
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units
RSP '05 Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping
ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
DDECS '06 Proceedings of the 2006 IEEE Design and Diagnostics of Electronic Circuits and systems
Using traditional loop unrolling to fit application on a new hybrid reconfigurable architecture
Proceedings of the 2008 ACM symposium on Applied computing
BRICK: a multi-context expression grained reconfigurable architecture
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
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The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. This paper presents RoSA, a coarse-grained reconfigurable architecture that combines compilation techniques and hardware reuse to accelerate the execution of stream-based applications. The results showed that RoSA achieved performance gains of more than 74% over the code that can be executed concurrently and 55% of the total cost of the applications.